The present invention relates to semiconductor device fabrication, particularly to self-aligned silicide (salicide) technology.
As gate electrode lengths are scaled down, the source and drain junctions and polycrystalline silicon line width must also be scaled down. However, scaling down the source and drain junctions and polycrystalline line width increases parasitic resistance in the source and drain diffusion layers and the gate electrode, and also increases the sheet and contact resistance of the gate electrode and source/drain regions.
Salicide technology comprises forming metal silicide layers on the source/drain regions and/or on the gate electrode of a semiconductor wafer in a self-aligned manner. A conventional approach to reduce resistivity involves forming a multi-layered structure comprising a low resistance refractory metal silicide layer on a doped polycrystalline silicon, typically referred to as a polycide. Salicide technology reduces parasitic sheet and contact resistance in the source and drain diffusion layers and the gate electrode that results from scaling down the source and drain junctions and polycrystalline silicon line width.
Silicides are typically formed by reacting a metal with silicon (Si) within a specified temperature range for a specific period of time. Silicide layers may be self-aligned by different techniques. For example, the metal can be selectively deposited on the gate electrode and on the source/drain regions, with subsequent annealing to react the metal with underlying Si in the source/drain regions and the gate electrode to form the metal silicide layers. Alternatively, sidewall spacers, e.g., silicon nitride or silicon dioxide, are formed on the side surfaces of the gate electrode, followed by a blanket deposition of metal and annealing to react the metal with Si in the gate electrode and the source/drain regions, while the sidewall spacers prevent metal reaction with Si from the side surfaces of the gate electrode.
During annealing, the wafer is heated to a reaction temperature and held at the reaction temperature for a period of time sufficient for the metal layer to react with underlying Si to form a metal silicide layer on the source/drain regions and the gate electrode. Multiple annealing steps may be employed.
Various metals react with Si to form a metal silicide; however, titanium (Ti) and cobalt (Co) are currently the most common metals used to create metal silicides when manufacturing semiconductor devices utilizing salicide technology. Recently, attention has turned towards nickel (Ni) to form nickel silicide utilizing salicide technology. Nickel silicide avoids many limitations associated with TiSi2 and CoSi2. Unlike Ti where Si diffuses into the metal layer when forming a Ti silicide, Ni, like Co, diffuses into Si, which helps to limit bridging between the metal silicide layer in the gate electrode and the metal silicide layer on the associated source/drain regions. The formation of nickel silicide requires less Si than TiSi2 and CoSi2. Nickel silicide also exhibits almost no line width dependence on sheet resistance. Nickel silicide is normally annealed in a one step process, vis-à-vis a process requiring an anneal, an etch, and a second anneal, as occurs in TiSi2 and CoSi2 saliciding. In addition, nickel silicide exhibits lower film stress, i.e., causes less wafer distortion, than conventional Ti or Co suicides.
Salicide processing efficiency is improved through the use of sidewall spacers. Sidewall spacers allow a blanket layer of metal to be deposited over the wafer surface. Sidewall spacers typically comprise silicon dioxide or silicon nitride, but silicon nitride sidewall spacers are often preferable because silicon nitride is highly conformal and the sidewall spacers can be added and removed as needed throughout the manufacturing process. However, the use of silicon nitride sidewall spacers with salicide technology results in bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions, particularly when Ni is used.
There is a need for salicide technology that avoids bridging between the metal silicide layer on the gate electrode and the metal silicide layers on the source/drain regions when using silicon nitride sidewall spacers, particularly when forming nickel salicide.
These and other needs are satisfied by embodiments of the present invention, which include a method of manufacturing a semiconductor device without bridging between a metal silicide layer, particularly nickel silicide, on the gate electrode and metal silicide layers, e.g., nickel silicide layers, on the source/drain regions using silicon-starved silicon nitride sidewall spacers. The method comprises supplying silane (SiH4) at a flow rate of approximately 100 sccm to approximately 250 sccm, supplying nitrogen (N2) at a flow rate of approximately 3,000 sccm to approximately 6,000 sccm, supplying ammonia (NH3) at a flow rate of approximately 2,000 sccm to approximately 4,000 sccm, applying radio frequency power of approximately 200 watts to approximately 350 watts, applying a pressure of approximately 1.6 torr to approximately 2.2 torr, and maintaining the temperature at approximately 360xc2x0 C. to approximately 380xc2x0 C.
The present invention advantageously limits metal bonding with Si in the silicon nitride sidewall spacers by reducing the availability of free Si in the sidewall spacers. Part of the silicidation process involves forming a metal silicide layer e.g., NiSi, on the polysilicon gate electrode and associated source/drain regions using salicide technology without bridging therebetween. In accordance with embodiments of the present invention, bridging is avoided by forming silicon-starved silicon nitride sidewall spacers, whereby the reduced Si in the silicon nitride sidewall spacers eliminates the free Si available to react with the metal subsequently deposited to form the metal silicide layer.
Other advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.